The namespace PoC.xil offers Xilinx specific implementations and abstractions
for various devices families.
migXilinx specific pre-configured memory controllers from Xilinx Memory Interface Generator (MIG).
The package PoC.xil holds all component declarations for this namespace.
xil_BSCANabstracts the boundary scan (JTAG) primitive of the following FPGA families:- Spartan-3, Spartan-6
- Virtex-5, Virtex-6
- 7-Series FPGAs.
xil_ChipScopeICONabstracts the ChipScope Integrated Controller (ICON) for 1 to 15 control ports. PoC provides 15 pre-configured IP core files (*.xco) to generate 15 netlists for all port counts.xil_ChipScopeICON_1- pre-configure netlist file for 1 portxil_ChipScopeICON_2- pre-configure netlist file for 2 portsxil_ChipScopeICON_3- pre-configure netlist file for 3 portsxil_ChipScopeICON_4- pre-configure netlist file for 4 portsxil_ChipScopeICON_5- pre-configure netlist file for 5 portsxil_ChipScopeICON_6- pre-configure netlist file for 6 portsxil_ChipScopeICON_7- pre-configure netlist file for 7 portsxil_ChipScopeICON_8- pre-configure netlist file for 8 portsxil_ChipScopeICON_9- pre-configure netlist file for 9 portsxil_ChipScopeICON_10- pre-configure netlist file for 10 portsxil_ChipScopeICON_11- pre-configure netlist file for 11 portsxil_ChipScopeICON_12- pre-configure netlist file for 12 portsxil_ChipScopeICON_13- pre-configure netlist file for 13 portsxil_ChipScopeICON_14- pre-configure netlist file for 14 portsxil_ChipScopeICON_15- pre-configure netlist file for 15 ports
xil_Reconfiguratorimplements generic reconfiguration module for the DRP bus, used by many Xilinx primitives like PLLs, DCMs or MGTs.xil_SystemMonitor_Virtex6- abstracts the Virtex-6 system monitor to measure the FPGA's temperature.xil_SystemMonitor_Series7- abstracts the 7-Series XADC primitive to measure the FPGA's temperature.