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VHDL-LS Linter generates an error with the select? statement #836

@scat00

Description

@scat00

Describe the bug
The vhdl default linter (VHDL-LS) generates an error with the select? statement.

select? statement is a uncommon but useful version of the select, introduced in VHDL 2008.
Which allows you to evaluate explicitly the don’t care (-), so It's useful to describe LUTs with don't care inputs.

References:

  • IEEE Std 1076-2008, IEEE Standard VHDL Language Reference Manual
  • Vivado Design Suite User Guide Synthesis, v2025.1
  • Circuit Design with VHDL Third Edition, Volnei A. Pedroni

To Reproduce

  1. Install TerosHDL
  2. Set VHDL Linter as: VHDL-LS
  3. Write a VHDL entity with a select? statement

Code

library ieee;
use ieee.std_logic_1164.all;

entity test is
  port (
    in1  : in std_logic_vector(3 downto 0);
    out1 : out std_logic_vector(3 downto 0)
  );
end entity;

architecture behavioral of test is
begin
  with in1 select?
    out1 <= "0100" when "000-",
            "0101" when "0-10",
            "0110" when "1010",
            "0000" when others;
end architecture;

Generated error by VHDL-LS Linter:
Expected '{identifier}', '{character}', '{string}' or 'all'

Please complete the following information:

  • OS: Rocky Linux 9.6
  • VSCode version: 1.106.1
  • TerosHDL version: 7.0.3 and 8.0.3

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