Is your feature request related to a problem? Please describe.
-: There is no problem currently in template generation, this is simply a feature request.
Describe the solution you'd like
-: I'd like the ability to either create my own templates, but specifically have the few following:
1. SystemVerilog testbench (replace reg/wire with logic).
2. Configure a different default delay for auto clock generation (#5 to something else)
3. Create an _assert.sv template, which flips the pin direction in an empty module for systemverilog assertions.
4. Include a bind in a systemverilog testbench between the _assert.sv and the dut
Is your feature request related to a problem? Please describe.
-: There is no problem currently in template generation, this is simply a feature request.
Describe the solution you'd like
-: I'd like the ability to either create my own templates, but specifically have the few following:
1. SystemVerilog testbench (replace reg/wire with logic).
2. Configure a different default delay for auto clock generation (#5 to something else)
3. Create an _assert.sv template, which flips the pin direction in an empty module for systemverilog assertions.
4. Include a bind in a systemverilog testbench between the _assert.sv and the dut