From b0f51f0d4b43d899115f25461f823936ee00de3a Mon Sep 17 00:00:00 2001 From: Qiaoyi Liu Date: Tue, 1 Mar 2022 23:15:48 -0800 Subject: [PATCH] add use_stub arg for wrapper gen --- lake/top/lake_top.py | 4 ++-- lake/utils/wrapper.py | 6 ++++++ 2 files changed, 8 insertions(+), 2 deletions(-) diff --git a/lake/top/lake_top.py b/lake/top/lake_top.py index 825cce34..b216db13 100644 --- a/lake/top/lake_top.py +++ b/lake/top/lake_top.py @@ -31,7 +31,7 @@ def __init__(self, interconnect_output_ports=2, mem_input_ports=1, mem_output_ports=1, - use_sram_stub=True, + use_sram_stub=False, sram_macro_info=SRAMMacroInfo("tsmc_name"), read_delay=1, # Cycle delay in read (SRAM vs Register File) rw_same_cycle=False, # Does the memory allow r+w in same cycle? @@ -113,7 +113,7 @@ def __init__(self, MTB.set_memory_interface(name_prefix=name_prefix, mem_params=memory_params, ports=tsmc_mem, - sim_macro_n=not self.use_sram_stub, + sim_macro_n=self.use_sram_stub, tech_map=tech_map) # Now add the controllers in... diff --git a/lake/utils/wrapper.py b/lake/utils/wrapper.py index f1a04b39..8185b136 100644 --- a/lake/utils/wrapper.py +++ b/lake/utils/wrapper.py @@ -105,6 +105,11 @@ def error(usage): help="use dual port sram", default=False) + parser.add_argument("-stub", + action='store_true', + help="use sram stub for clockwork verilator simulation", + default=True) + parser.add_argument("-v", action='store_true', help='Generate main verilog') @@ -156,6 +161,7 @@ def error(usage): lake_kwargs['mem_depth'] = args.d lake_kwargs['rw_same_cycle'] = args.dp lake_kwargs['input_iterator_support'] = args.ii + lake_kwargs['use_sram_stub'] = args.stub lake_kwargs['output_iterator_support'] = args.oi lake_kwargs['read_delay'] = args.rd lake_kwargs['name'] = args.vmn