From 12794a95d149e01a1b5f73955cbf6747e5f9997f Mon Sep 17 00:00:00 2001 From: Kavya Sreedhar Date: Sat, 9 Jan 2021 15:06:23 -0800 Subject: [PATCH 01/17] add addressor info to system + print_verilog from frail in gen verilog --- lake/dsl/dsl_examples/memtile.py | 25 ++++++++++++++++++++++++- lake/dsl/hw_top_lake.py | 3 ++- lake/dsl/top_lake.py | 24 +++++++++++++++++++++++- 3 files changed, 49 insertions(+), 3 deletions(-) diff --git a/lake/dsl/dsl_examples/memtile.py b/lake/dsl/dsl_examples/memtile.py index 5052b33b..252dce93 100644 --- a/lake/dsl/dsl_examples/memtile.py +++ b/lake/dsl/dsl_examples/memtile.py @@ -1,4 +1,5 @@ from lake.dsl.lake_imports import * +from frail.ast import * # example of DSL (makes current mem tile with 2 agg, # wide SRAM, 2 tb @@ -7,9 +8,31 @@ # IMPORTANT: PORTS MUST BE INSTANTIATED BEFORE MEMORIES # MEMORIES SHOULD BE INSTANTIATED BEFORE EDGES +# addressor in frail + +# configuration registers +x_max = var_f("x_max") +y_max = var_f("y_max") +x_stride = var_f("x_stride") +y_stride = var_f("y_stride") +offset = var_f("offset") + +# original addressor design +def create_og_design(): + x_unit_counter = scan_const_f(lambda z: if_f(eq_f(z, sub_f(x_max, int_f(1))), int_f(0), add_f(z, int_f(1)))) + y_unit_counter = scan_const_f(lambda z: if_f(eq_f(x_unit_counter.get_seq(), sub_f(x_max, int_f(1))), add_f(z, int_f(1)), z)) + x_counter = scan_const_f(lambda z: if_f(eq_f(x_unit_counter.get_seq(), sub_f(x_max, int_f(1))), int_f(0), add_f(z, x_stride))) + y_counter = scan_const_f(lambda z: if_f(eq_f(x_unit_counter.get_seq(), sub_f(x_max, int_f(1))), add_f(z, y_stride), z)) + og_design = scan_const_f(lambda z: add_f(add_f(x_counter.get_seq(), y_counter.get_seq()), offset)) + return og_design + +og_design = create_og_design() + # word_width, input_ports, output_ports tile = Lake(16, 2, 2) +tile.set_addressor(og_design, "og_design") + # MemPort attributes are latency, initiation interval agg_write_port = MemPort(1, 0) agg_read_port = MemPort(0, 0) @@ -48,4 +71,4 @@ tile.add_edge("sram", "tb1") # for both compiler collateral and HW generation -# tile.construct_lake("memtile.sv") +tile.construct_lake("memtile.sv") diff --git a/lake/dsl/hw_top_lake.py b/lake/dsl/hw_top_lake.py index 0cbca2e0..ca050b09 100644 --- a/lake/dsl/hw_top_lake.py +++ b/lake/dsl/hw_top_lake.py @@ -23,7 +23,8 @@ def __init__(self, input_ports, output_ports, memories, - edges): + edges, + addressor): super().__init__("LakeTop", debug=True) diff --git a/lake/dsl/top_lake.py b/lake/dsl/top_lake.py index dcb5407d..541756df 100644 --- a/lake/dsl/top_lake.py +++ b/lake/dsl/top_lake.py @@ -1,4 +1,5 @@ import copy +import sys from lake.dsl.memory import mem_inst, port_to_info from lake.dsl.edge import edge_inst, get_full_edge_params @@ -8,6 +9,8 @@ from lake.passes.passes import change_sram_port_names from lake.modules.cfg_reg_wrapper import CFGRegWrapper +from frail.verilog_printer import * + class Lake(): def __init__(self, @@ -34,6 +37,10 @@ def __init__(self, self.hw_edges = [] self.hardware_edges = [] + self.addressor_info = {"use_default": True, + "addressor": None, + "name": "top"} + # mux info originally created for hardware, but not used # keeping here in case logic is useful for the future self.mux_count = 0 @@ -99,6 +106,11 @@ def add_input_output_edge(self, port, mem_name, dim=6, max_range=65536, max_stri self.memories[mem_name][f"is_{io}"] = True self.memories[mem_name][f"{io}_port"] = port + def set_addressor(self, addressor=None, name="top"): + self.addressor_info = {"use_default": True if addressor is None else False, + "addressor": addressor, + "name": name} + # called after all edges are added def banking(self): self.hw_memories = copy.deepcopy(self.memories) @@ -267,7 +279,8 @@ def generate_hardware(self, wrap_cfg=True): self.input_ports, self.output_ports, self.hw_memories, - self.hardware_edges) + self.hardware_edges, + self.addressor_info) # Wrap it if we need to... if wrap_cfg: @@ -295,3 +308,12 @@ def construct_lake(self, filename="Lake_hw.sv", wrap_cfg=False): optimize_if=False, check_flip_flop_always_ff=False, additional_passes={"change sram port names": sram_port_pass}) + + if not self.addressor_info["use_default"]: + with open(filename, "a") as fi: + orig_stdout = sys.stdout + sys.stdout = fi + print_verilog(self.addressor_info["addressor"], + top_name=self.addressor_info["name"], + add_step=True) + sys.stdout = orig_stdout \ No newline at end of file From c4e2e732e3ff90531886db8017367a6d234472e7 Mon Sep 17 00:00:00 2001 From: Kavya Sreedhar Date: Sat, 9 Jan 2021 17:11:54 -0800 Subject: [PATCH 02/17] default addr usage proof of concept --- lake/dsl/hw_top_lake.py | 47 +++++++++++++++++++++++++++++------------ 1 file changed, 34 insertions(+), 13 deletions(-) diff --git a/lake/dsl/hw_top_lake.py b/lake/dsl/hw_top_lake.py index ca050b09..bd90837e 100644 --- a/lake/dsl/hw_top_lake.py +++ b/lake/dsl/hw_top_lake.py @@ -10,6 +10,7 @@ from lake.dsl.memory import mem_inst from lake.modules.for_loop import ForLoop from lake.modules.addr_gen import AddrGen +from lake.modules.addressor import Addressor from lake.modules.spec.sched_gen import SchedGen from lake.passes.passes import lift_config_reg from lake.utils.util import safe_wire, trim_config_list @@ -24,7 +25,7 @@ def __init__(self, output_ports, memories, edges, - addressor): + addressor_info): super().__init__("LakeTop", debug=True) @@ -42,6 +43,12 @@ def __init__(self, self.memories = memories self.edges = edges + # addressor_info + self.use_default_addr = addressor_info["use_default"] + if not self.use_default_addr: + self.addressor = addressor_info["addressor"] + self.addressor_name = addressor_info["name"] + # tile enable and clock self.tile_en = self.input("tile_en", 1) self.tile_en.add_attribute(ConfigRegAttr("Tile logic enable manifested as clock gate")) @@ -185,20 +192,34 @@ def increment_cycle_count(self): rst_n=self.rst_n, step=self.valid) - newAG = AddrGen(iterator_support=input_dim, - config_width=max(1, clog2(input_stride))) # self.default_config_width) - self.add_child(f"input_port{input_port_index}_2{in_mem}_write_addr_gen", - newAG, - clk=self.gclk, - rst_n=self.rst_n, - step=self.valid, - mux_sel=forloop.ports.mux_sel_out, - restart=forloop.ports.restart) + if self.use_default_addr: + newAG = AddrGen(iterator_support=input_dim, + config_width=max(1, clog2(input_stride))) # self.default_config_width) + self.add_child(f"input_port{input_port_index}_2{in_mem}_write_addr_gen", + newAG, + clk=self.gclk, + rst_n=self.rst_n, + step=self.valid, + mux_sel=forloop.ports.mux_sel_out, + restart=forloop.ports.restart) + + if self.memories[in_mem]["num_read_write_ports"] == 0: + safe_wire(self, self.mem_insts[in_mem].ports.write_addr[0], newAG.ports.addr_out) + else: + self.mem_read_write_addrs[in_mem]["write_addr"] = newAG.ports.addr_out - if self.memories[in_mem]["num_read_write_ports"] == 0: - safe_wire(self, self.mem_insts[in_mem].ports.write_addr[0], newAG.ports.addr_out) else: - self.mem_read_write_addrs[in_mem]["write_addr"] = newAG.ports.addr_out + newAG = Addressor(self.addressor_name) + self.add_child(f"input_port{input_port_index}_2{in_mem}_write_addr_gen", + newAG, + clk=self.gclk, + step=self.valid) + + if self.memories[in_mem]["num_read_write_ports"] == 0: + safe_wire(self, self.mem_insts[in_mem].ports.write_addr[0], newAG.ports.addr) + else: + self.mem_read_write_addrs[in_mem]["write_addr"] = newAG.ports.addr + newSG = SchedGen(iterator_support=input_dim, config_width=self.cycle_count_width) From 8e1def8fc51be7a47054cf947f11291c79a63f32 Mon Sep 17 00:00:00 2001 From: Kavya Sreedhar Date: Sat, 9 Jan 2021 18:48:45 -0800 Subject: [PATCH 03/17] wrote opdesign6 addressor, have config lift working with addressor wrapper and external module automatically generated from frail --- lake/dsl/dsl_examples/memtile.py | 42 ++++++++++++++++++++------------ lake/dsl/hw_top_lake.py | 24 +++++++++--------- lake/passes/passes.py | 1 + 3 files changed, 39 insertions(+), 28 deletions(-) diff --git a/lake/dsl/dsl_examples/memtile.py b/lake/dsl/dsl_examples/memtile.py index 252dce93..1abd8148 100644 --- a/lake/dsl/dsl_examples/memtile.py +++ b/lake/dsl/dsl_examples/memtile.py @@ -9,29 +9,39 @@ # MEMORIES SHOULD BE INSTANTIATED BEFORE EDGES # addressor in frail +# original addressor design -# configuration registers -x_max = var_f("x_max") -y_max = var_f("y_max") -x_stride = var_f("x_stride") -y_stride = var_f("y_stride") -offset = var_f("offset") -# original addressor design -def create_og_design(): - x_unit_counter = scan_const_f(lambda z: if_f(eq_f(z, sub_f(x_max, int_f(1))), int_f(0), add_f(z, int_f(1)))) - y_unit_counter = scan_const_f(lambda z: if_f(eq_f(x_unit_counter.get_seq(), sub_f(x_max, int_f(1))), add_f(z, int_f(1)), z)) - x_counter = scan_const_f(lambda z: if_f(eq_f(x_unit_counter.get_seq(), sub_f(x_max, int_f(1))), int_f(0), add_f(z, x_stride))) - y_counter = scan_const_f(lambda z: if_f(eq_f(x_unit_counter.get_seq(), sub_f(x_max, int_f(1))), add_f(z, y_stride), z)) - og_design = scan_const_f(lambda z: add_f(add_f(x_counter.get_seq(), y_counter.get_seq()), offset)) - return og_design +def create_og_design6(): + + # configuration registers + r0, r1, r2, r3, r4, r5 = var_f("range_0"), var_f("range_1"), var_f("range_2"), var_f("range_3"), var_f("range_4"), var_f("range_5") + s0, s1, s2, s3, s4, s5 = var_f("stride_0"), var_f("stride_1"), var_f("stride_2"), var_f("stride_3"), var_f("stride_4"), var_f("stride_5") + offset = var_f("offset") + + uc0 = scan_const_f(lambda z: if_f(eq_f(z, sub_f(r0, int_f(1))), int_f(0), add_f(z, int_f(1)))) + uc1 = scan_const_f(lambda z: if_f(eq_f(uc0.get_seq(), sub_f(r0, int_f(1))), add_f(z, int_f(1)), z)) + uc2 = scan_const_f(lambda z: if_f(eq_f(uc1.get_seq(), sub_f(r1, int_f(1))), add_f(z, int_f(1)), z)) + uc3 = scan_const_f(lambda z: if_f(eq_f(uc2.get_seq(), sub_f(r2, int_f(1))), add_f(z, int_f(1)), z)) + uc4 = scan_const_f(lambda z: if_f(eq_f(uc3.get_seq(), sub_f(r3, int_f(1))), add_f(z, int_f(1)), z)) + uc5 = scan_const_f(lambda z: if_f(eq_f(uc4.get_seq(), sub_f(r4, int_f(1))), add_f(z, int_f(1)), z)) + + c0 = scan_const_f(lambda z: if_f(eq_f(uc0.get_seq(), sub_f(r0, int_f(1))), int_f(0), add_f(z, s0))) + c1 = scan_const_f(lambda z: if_f(eq_f(uc0.get_seq(), sub_f(r0, int_f(1))), add_f(z, s1), z)) + c2 = scan_const_f(lambda z: if_f(eq_f(uc1.get_seq(), sub_f(r1, int_f(1))), add_f(z, s2), z)) + c3 = scan_const_f(lambda z: if_f(eq_f(uc2.get_seq(), sub_f(r2, int_f(1))), add_f(z, s3), z)) + c4 = scan_const_f(lambda z: if_f(eq_f(uc3.get_seq(), sub_f(r3, int_f(1))), add_f(z, s4), z)) + c5 = scan_const_f(lambda z: if_f(eq_f(uc4.get_seq(), sub_f(r4, int_f(1))), add_f(z, s5), z)) + + return scan_const_f(lambda z: add_f(offset, add_f(c0.get_seq(), add_f(c1.get_seq(), add_f(c2.get_seq(), add_f(c3.get_seq(), add_f(c4.get_seq(), c5.get_seq()))))))) + -og_design = create_og_design() +og_design6 = create_og_design6() # word_width, input_ports, output_ports tile = Lake(16, 2, 2) -tile.set_addressor(og_design, "og_design") +tile.set_addressor(og_design6, "og_design6") # MemPort attributes are latency, initiation interval agg_write_port = MemPort(1, 0) diff --git a/lake/dsl/hw_top_lake.py b/lake/dsl/hw_top_lake.py index bd90837e..2018a4ca 100644 --- a/lake/dsl/hw_top_lake.py +++ b/lake/dsl/hw_top_lake.py @@ -10,7 +10,7 @@ from lake.dsl.memory import mem_inst from lake.modules.for_loop import ForLoop from lake.modules.addr_gen import AddrGen -from lake.modules.addressor import Addressor +from lake.modules.addressor import * from lake.modules.spec.sched_gen import SchedGen from lake.passes.passes import lift_config_reg from lake.utils.util import safe_wire, trim_config_list @@ -196,12 +196,12 @@ def increment_cycle_count(self): newAG = AddrGen(iterator_support=input_dim, config_width=max(1, clog2(input_stride))) # self.default_config_width) self.add_child(f"input_port{input_port_index}_2{in_mem}_write_addr_gen", - newAG, - clk=self.gclk, - rst_n=self.rst_n, - step=self.valid, - mux_sel=forloop.ports.mux_sel_out, - restart=forloop.ports.restart) + newAG, + clk=self.gclk, + rst_n=self.rst_n, + step=self.valid, + mux_sel=forloop.ports.mux_sel_out, + restart=forloop.ports.restart) if self.memories[in_mem]["num_read_write_ports"] == 0: safe_wire(self, self.mem_insts[in_mem].ports.write_addr[0], newAG.ports.addr_out) @@ -209,17 +209,16 @@ def increment_cycle_count(self): self.mem_read_write_addrs[in_mem]["write_addr"] = newAG.ports.addr_out else: - newAG = Addressor(self.addressor_name) + newAG = AddressorWrapper(self.addressor_name) self.add_child(f"input_port{input_port_index}_2{in_mem}_write_addr_gen", - newAG, - clk=self.gclk, - step=self.valid) + newAG, + clk=self.gclk, + step=self.valid) if self.memories[in_mem]["num_read_write_ports"] == 0: safe_wire(self, self.mem_insts[in_mem].ports.write_addr[0], newAG.ports.addr) else: self.mem_read_write_addrs[in_mem]["write_addr"] = newAG.ports.addr - newSG = SchedGen(iterator_support=input_dim, config_width=self.cycle_count_width) @@ -504,6 +503,7 @@ def get_delayed_write(self): flush_port = self.internal_generator.get_port("flush") # bring config registers up to top level + lift_config_reg(self.internal_generator) # formal subproblem annotations - uncomment to generate relevant files diff --git a/lake/passes/passes.py b/lake/passes/passes.py index 40d0d5c6..40f8a5cd 100644 --- a/lake/passes/passes.py +++ b/lake/passes/passes.py @@ -20,6 +20,7 @@ def __init__(self): IRVisitor.__init__(self) def visit(self, node): + # doesn't include external nodes... if isinstance(node, _kratos.Generator): ports_ = node.get_port_names() for port_name in ports_: From b2d46d286a7487651f1620b526b9b447d82b9fec Mon Sep 17 00:00:00 2001 From: Kavya Sreedhar Date: Sat, 9 Jan 2021 19:19:50 -0800 Subject: [PATCH 04/17] addressor import happens after addressor file updated --- lake/dsl/top_lake.py | 29 +++++++++++++++++++++-------- 1 file changed, 21 insertions(+), 8 deletions(-) diff --git a/lake/dsl/top_lake.py b/lake/dsl/top_lake.py index 541756df..a45d7e5f 100644 --- a/lake/dsl/top_lake.py +++ b/lake/dsl/top_lake.py @@ -1,10 +1,11 @@ import copy import sys +import pathlib from lake.dsl.memory import mem_inst, port_to_info from lake.dsl.edge import edge_inst, get_full_edge_params from lake.dsl.helper import * -from lake.dsl.hw_top_lake import TopLakeHW + from lake.utils.sram_macro import SRAMMacroInfo from lake.passes.passes import change_sram_port_names from lake.modules.cfg_reg_wrapper import CFGRegWrapper @@ -111,6 +112,11 @@ def set_addressor(self, addressor=None, name="top"): "addressor": addressor, "name": name} + if not self.addressor_info["use_default"]: + lake_dir = pathlib.Path(__file__).parent.parent.absolute() + addr_file = f"{lake_dir}/modules/addressor.py" + self.print_verilog_helper(addr_file, "w+", False) + # called after all edges are added def banking(self): self.hw_memories = copy.deepcopy(self.memories) @@ -275,6 +281,9 @@ def generate_hardware(self, wrap_cfg=True): # print() # print(self.hardware_edges) + # need this import to contain updated frail addressor + from lake.dsl.hw_top_lake import TopLakeHW + hw = TopLakeHW(self.word_width, self.input_ports, self.output_ports, @@ -310,10 +319,14 @@ def construct_lake(self, filename="Lake_hw.sv", wrap_cfg=False): additional_passes={"change sram port names": sram_port_pass}) if not self.addressor_info["use_default"]: - with open(filename, "a") as fi: - orig_stdout = sys.stdout - sys.stdout = fi - print_verilog(self.addressor_info["addressor"], - top_name=self.addressor_info["name"], - add_step=True) - sys.stdout = orig_stdout \ No newline at end of file + self.print_verilog_helper(filename, "a", True) + + def print_verilog_helper(self, filename, mode, get_verilog): + with open(filename, mode) as fi: + orig_stdout = sys.stdout + sys.stdout = fi + print_verilog(self.addressor_info["addressor"], + top_name=self.addressor_info["name"], + add_step=True, + get_verilog=get_verilog) + sys.stdout = orig_stdout \ No newline at end of file From a94623674e3fec90863a55079078e92448a66d73 Mon Sep 17 00:00:00 2001 From: Kavya Sreedhar Date: Sat, 9 Jan 2021 20:35:49 -0800 Subject: [PATCH 05/17] use same addressor names as wo frail to use same lake tb --- lake/dsl/dsl_examples/memtile.py | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/lake/dsl/dsl_examples/memtile.py b/lake/dsl/dsl_examples/memtile.py index 1abd8148..dfeed6c3 100644 --- a/lake/dsl/dsl_examples/memtile.py +++ b/lake/dsl/dsl_examples/memtile.py @@ -15,9 +15,9 @@ def create_og_design6(): # configuration registers - r0, r1, r2, r3, r4, r5 = var_f("range_0"), var_f("range_1"), var_f("range_2"), var_f("range_3"), var_f("range_4"), var_f("range_5") - s0, s1, s2, s3, s4, s5 = var_f("stride_0"), var_f("stride_1"), var_f("stride_2"), var_f("stride_3"), var_f("stride_4"), var_f("stride_5") - offset = var_f("offset") + r0, r1, r2, r3, r4, r5 = var_f("ranges_0"), var_f("ranges_1"), var_f("ranges_2"), var_f("ranges_3"), var_f("ranges_4"), var_f("ranges_5") + s0, s1, s2, s3, s4, s5 = var_f("strides_0"), var_f("strides_1"), var_f("strides_2"), var_f("strides_3"), var_f("strides_4"), var_f("strides_5") + offset = var_f("starting_addr") uc0 = scan_const_f(lambda z: if_f(eq_f(z, sub_f(r0, int_f(1))), int_f(0), add_f(z, int_f(1)))) uc1 = scan_const_f(lambda z: if_f(eq_f(uc0.get_seq(), sub_f(r0, int_f(1))), add_f(z, int_f(1)), z)) @@ -81,4 +81,4 @@ def create_og_design6(): tile.add_edge("sram", "tb1") # for both compiler collateral and HW generation -tile.construct_lake("memtile.sv") +# tile.construct_lake("memtile.sv") From 9e031ba9e34a3a1929c791177ade3274e8de2086 Mon Sep 17 00:00:00 2001 From: Kavya Sreedhar Date: Sat, 9 Jan 2021 20:49:04 -0800 Subject: [PATCH 06/17] successfully running dsl test with frail addressor imported in --- tests/test_dsl_memtile.py | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/tests/test_dsl_memtile.py b/tests/test_dsl_memtile.py index 1d2de549..7bdf2763 100644 --- a/tests/test_dsl_memtile.py +++ b/tests/test_dsl_memtile.py @@ -3,6 +3,7 @@ import pytest import tempfile import os +import shutil from lake.passes.passes import lift_config_reg, change_sram_port_names from lake.utils.sram_macro import SRAMMacroInfo @@ -40,6 +41,7 @@ def base_lake_tester(config_path, def gen_test_lake(config_path, stream_path, lt_dut, + tile, in_file_name="input", out_file_name="output", in_ports=2, @@ -85,6 +87,10 @@ def gen_test_lake(config_path, with tempfile.TemporaryDirectory() as tempdir: tempdir = "hw" + if not tile.addressor_info["use_default"]: + addr_verilog = tile.addressor_info["name"] + ".v" + tile.print_verilog_helper(addr_verilog, "w+", True) + shutil.copy(addr_verilog, tempdir) tester.compile_and_run(target="verilator", directory=tempdir, flags=["-Wno-fatal", "--trace"]) @@ -99,7 +105,8 @@ def test_conv_3_3(): gen_test_lake(config_path=config_path, stream_path=stream_path, - lt_dut=lt_dut) + lt_dut=lt_dut, + tile=tile) if __name__ == "__main__": From 1a0bc192017a520a1f6908726ea2c52b057ae7d5 Mon Sep 17 00:00:00 2001 From: Kavya Sreedhar Date: Sun, 10 Jan 2021 14:12:49 -0800 Subject: [PATCH 07/17] testing frail addr integration in lake dsl --- lake/dsl/dsl_examples/memtile.py | 68 +++++++------- lake/dsl/hw_top_lake.py | 139 +++++++++++++++++++---------- lake/utils/parse_clkwork_config.py | 17 +++- tests/test_dsl_memtile.py | 6 +- 4 files changed, 146 insertions(+), 84 deletions(-) diff --git a/lake/dsl/dsl_examples/memtile.py b/lake/dsl/dsl_examples/memtile.py index dfeed6c3..aecf3a4a 100644 --- a/lake/dsl/dsl_examples/memtile.py +++ b/lake/dsl/dsl_examples/memtile.py @@ -8,41 +8,9 @@ # IMPORTANT: PORTS MUST BE INSTANTIATED BEFORE MEMORIES # MEMORIES SHOULD BE INSTANTIATED BEFORE EDGES -# addressor in frail -# original addressor design - - -def create_og_design6(): - - # configuration registers - r0, r1, r2, r3, r4, r5 = var_f("ranges_0"), var_f("ranges_1"), var_f("ranges_2"), var_f("ranges_3"), var_f("ranges_4"), var_f("ranges_5") - s0, s1, s2, s3, s4, s5 = var_f("strides_0"), var_f("strides_1"), var_f("strides_2"), var_f("strides_3"), var_f("strides_4"), var_f("strides_5") - offset = var_f("starting_addr") - - uc0 = scan_const_f(lambda z: if_f(eq_f(z, sub_f(r0, int_f(1))), int_f(0), add_f(z, int_f(1)))) - uc1 = scan_const_f(lambda z: if_f(eq_f(uc0.get_seq(), sub_f(r0, int_f(1))), add_f(z, int_f(1)), z)) - uc2 = scan_const_f(lambda z: if_f(eq_f(uc1.get_seq(), sub_f(r1, int_f(1))), add_f(z, int_f(1)), z)) - uc3 = scan_const_f(lambda z: if_f(eq_f(uc2.get_seq(), sub_f(r2, int_f(1))), add_f(z, int_f(1)), z)) - uc4 = scan_const_f(lambda z: if_f(eq_f(uc3.get_seq(), sub_f(r3, int_f(1))), add_f(z, int_f(1)), z)) - uc5 = scan_const_f(lambda z: if_f(eq_f(uc4.get_seq(), sub_f(r4, int_f(1))), add_f(z, int_f(1)), z)) - - c0 = scan_const_f(lambda z: if_f(eq_f(uc0.get_seq(), sub_f(r0, int_f(1))), int_f(0), add_f(z, s0))) - c1 = scan_const_f(lambda z: if_f(eq_f(uc0.get_seq(), sub_f(r0, int_f(1))), add_f(z, s1), z)) - c2 = scan_const_f(lambda z: if_f(eq_f(uc1.get_seq(), sub_f(r1, int_f(1))), add_f(z, s2), z)) - c3 = scan_const_f(lambda z: if_f(eq_f(uc2.get_seq(), sub_f(r2, int_f(1))), add_f(z, s3), z)) - c4 = scan_const_f(lambda z: if_f(eq_f(uc3.get_seq(), sub_f(r3, int_f(1))), add_f(z, s4), z)) - c5 = scan_const_f(lambda z: if_f(eq_f(uc4.get_seq(), sub_f(r4, int_f(1))), add_f(z, s5), z)) - - return scan_const_f(lambda z: add_f(offset, add_f(c0.get_seq(), add_f(c1.get_seq(), add_f(c2.get_seq(), add_f(c3.get_seq(), add_f(c4.get_seq(), c5.get_seq()))))))) - - -og_design6 = create_og_design6() - # word_width, input_ports, output_ports tile = Lake(16, 2, 2) -tile.set_addressor(og_design6, "og_design6") - # MemPort attributes are latency, initiation interval agg_write_port = MemPort(1, 0) agg_read_port = MemPort(0, 0) @@ -80,5 +48,41 @@ def create_og_design6(): tile.add_edge("sram", "tb") tile.add_edge("sram", "tb1") +# addressor in frail +# original addressor design + +def create_og_design6(): + + # configuration registers + r0, r1, r2, r3, r4, r5 = var_f("ranges_0"), var_f("ranges_1"), var_f("ranges_2"), var_f("ranges_3"), var_f("ranges_4"), var_f("ranges_5") + s0, s1, s2, s3, s4, s5 = var_f("strides_0"), var_f("strides_1"), var_f("strides_2"), var_f("strides_3"), var_f("strides_4"), var_f("strides_5") + dim = var_f("dimensionality") + offset = var_f("starting_addr") + + uc0 = scan_const_f(lambda z: if_f(eq_f(z, sub_f(r0, int_f(1))), int_f(0), add_f(z, int_f(1)))) + uc0 = scan_const_f(lambda z: if_f(eq_f(dim, int_f(0)), int_f(0), uc0.get_seq())) + uc1 = scan_const_f(lambda z: if_f(eq_f(uc0.get_seq(), sub_f(r0, int_f(1))), add_f(z, int_f(1)), z)) + uc1 = scan_const_f(lambda z: if_f(eq_f(dim, int_f(1)), int_f(0), uc1.get_seq())) + uc2 = scan_const_f(lambda z: if_f(eq_f(uc1.get_seq(), sub_f(r1, int_f(1))), add_f(z, int_f(1)), z)) + uc2 = scan_const_f(lambda z: if_f(eq_f(dim, int_f(2)), int_f(0), uc2.get_seq())) + uc3 = scan_const_f(lambda z: if_f(eq_f(uc2.get_seq(), sub_f(r2, int_f(1))), add_f(z, int_f(1)), z)) + uc3 = scan_const_f(lambda z: if_f(eq_f(dim, int_f(3)), int_f(0), uc3.get_seq())) + uc4 = scan_const_f(lambda z: if_f(eq_f(uc3.get_seq(), sub_f(r3, int_f(1))), add_f(z, int_f(1)), z)) + uc4 = scan_const_f(lambda z: if_f(eq_f(dim, int_f(4)), int_f(0), uc4.get_seq())) + uc5 = scan_const_f(lambda z: if_f(eq_f(uc4.get_seq(), sub_f(r4, int_f(1))), add_f(z, int_f(1)), z)) + uc5 = scan_const_f(lambda z: if_f(eq_f(dim, int_f(5)), int_f(0), uc5.get_seq())) + + c0 = scan_const_f(lambda z: if_f(eq_f(uc0.get_seq(), sub_f(r0, int_f(1))), int_f(0), add_f(z, s0))) + c1 = scan_const_f(lambda z: if_f(eq_f(uc0.get_seq(), sub_f(r0, int_f(1))), add_f(z, s1), z)) + c2 = scan_const_f(lambda z: if_f(eq_f(uc1.get_seq(), sub_f(r1, int_f(1))), add_f(z, s2), z)) + c3 = scan_const_f(lambda z: if_f(eq_f(uc2.get_seq(), sub_f(r2, int_f(1))), add_f(z, s3), z)) + c4 = scan_const_f(lambda z: if_f(eq_f(uc3.get_seq(), sub_f(r3, int_f(1))), add_f(z, s4), z)) + c5 = scan_const_f(lambda z: if_f(eq_f(uc4.get_seq(), sub_f(r4, int_f(1))), add_f(z, s5), z)) + + return scan_const_f(lambda z: add_f(offset, add_f(c0.get_seq(), add_f(c1.get_seq(), add_f(c2.get_seq(), add_f(c3.get_seq(), add_f(c4.get_seq(), c5.get_seq()))))))) + +og_design6 = create_og_design6() +tile.set_addressor(og_design6, "og_design6") + # for both compiler collateral and HW generation # tile.construct_lake("memtile.sv") diff --git a/lake/dsl/hw_top_lake.py b/lake/dsl/hw_top_lake.py index 2018a4ca..22eebb57 100644 --- a/lake/dsl/hw_top_lake.py +++ b/lake/dsl/hw_top_lake.py @@ -203,11 +203,6 @@ def increment_cycle_count(self): mux_sel=forloop.ports.mux_sel_out, restart=forloop.ports.restart) - if self.memories[in_mem]["num_read_write_ports"] == 0: - safe_wire(self, self.mem_insts[in_mem].ports.write_addr[0], newAG.ports.addr_out) - else: - self.mem_read_write_addrs[in_mem]["write_addr"] = newAG.ports.addr_out - else: newAG = AddressorWrapper(self.addressor_name) self.add_child(f"input_port{input_port_index}_2{in_mem}_write_addr_gen", @@ -215,10 +210,10 @@ def increment_cycle_count(self): clk=self.gclk, step=self.valid) - if self.memories[in_mem]["num_read_write_ports"] == 0: - safe_wire(self, self.mem_insts[in_mem].ports.write_addr[0], newAG.ports.addr) - else: - self.mem_read_write_addrs[in_mem]["write_addr"] = newAG.ports.addr + if self.memories[in_mem]["num_read_write_ports"] == 0: + safe_wire(self, self.mem_insts[in_mem].ports.write_addr[0], newAG.ports.addr_out) + else: + self.mem_read_write_addrs[in_mem]["write_addr"] = newAG.ports.addr_out newSG = SchedGen(iterator_support=input_dim, config_width=self.cycle_count_width) @@ -264,16 +259,24 @@ def increment_cycle_count(self): rst_n=self.rst_n, step=self.valid) - newAG = AddrGen(iterator_support=output_dim, - config_width=max(1, clog2(output_stride))) # self.default_config_width) - self.add_child(f"{out_mem}2output_port{output_port_index}_read_addr_gen", - newAG, - clk=self.gclk, - rst_n=self.rst_n, - step=self.valid, - mux_sel=forloop.ports.mux_sel_out, - restart=forloop.ports.restart) + if self.use_default_addr: + newAG = AddrGen(iterator_support=output_dim, + config_width=max(1, clog2(output_stride))) # self.default_config_width) + self.add_child(f"{out_mem}2output_port{output_port_index}_read_addr_gen", + newAG, + clk=self.gclk, + rst_n=self.rst_n, + step=self.valid, + mux_sel=forloop.ports.mux_sel_out, + restart=forloop.ports.restart) + else: + newAG = AddressorWrapper(self.addressor_name) + self.add_child(f"{out_mem}2output_port{output_port_index}_read_addr_gen", + newAG, + clk=self.gclk, + step=self.valid) + if self.memories[out_mem]["num_read_write_ports"] == 0: safe_wire(self, self.mem_insts[out_mem].ports.read_addr[0], newAG.ports.addr_out) else: @@ -317,15 +320,22 @@ def increment_cycle_count(self): step=self.valid) # create input addressor - readAG = AddrGen(iterator_support=edge["dim"], - config_width=self.default_config_width) - self.add_child(f"{edge_name}_read_addr_gen", - readAG, - clk=self.gclk, - rst_n=self.rst_n, - step=self.valid, - mux_sel=forloop.ports.mux_sel_out, - restart=forloop.ports.restart) + if self.use_default_addr: + readAG = AddrGen(iterator_support=edge["dim"], + config_width=self.default_config_width) + self.add_child(f"{edge_name}_read_addr_gen", + readAG, + clk=self.gclk, + rst_n=self.rst_n, + step=self.valid, + mux_sel=forloop.ports.mux_sel_out, + restart=forloop.ports.restart) + else: + readAG = AddressorWrapper(self.addressor_name) + self.add_child(f"{edge_name}_read_addr_gen", + readAG, + clk=self.gclk, + step=self.valid) # assign read address to all from memories if self.memories[edge["from_signal"][0]]["num_read_write_ports"] == 0: @@ -372,13 +382,20 @@ def increment_cycle_count(self): self.mem_insts[edge["from_signal"][0]].ports.data_out) # create output addressor - writeAG = AddrGen(iterator_support=edge["dim"], - config_width=self.default_config_width) - # step, mux_sel, restart may need delayed signals (assigned later) - self.add_child(f"{edge_name}_write_addr_gen", - writeAG, - clk=self.gclk, - rst_n=self.rst_n) + if self.use_default_addr: + writeAG = AddrGen(iterator_support=edge["dim"], + config_width=self.default_config_width) + # step, mux_sel, restart may need delayed signals (assigned later) + self.add_child(f"{edge_name}_write_addr_gen", + writeAG, + clk=self.gclk, + rst_n=self.rst_n) + else: + writeAG = AddressorWrapper(self.addressor_name) + self.add_child(f"{edge_name}_write_addr_gen", + writeAG, + clk=self.gclk, + step=self.valid) # set write addr for to memories if self.memories[edge["to_signal"][0]]["num_read_write_ports"] == 0: @@ -461,12 +478,14 @@ def get_delayed_write(self): # assign delayed signals for write addressor if needed if self.delay == 0: self.wire(writeAG.ports.step, self.valid) - self.wire(writeAG.ports.mux_sel, self.forloop.ports.mux_sel_out) - self.wire(writeAG.ports.restart, self.forloop.ports.restart) + if self.use_default_addr: + self.wire(writeAG.ports.mux_sel, self.forloop.ports.mux_sel_out) + self.wire(writeAG.ports.restart, self.forloop.ports.restart) else: self.wire(writeAG.ports.step, self.delayed_writes[self.delay - 1]) - self.wire(writeAG.ports.mux_sel, self.delayed_mux_sels[self.delay - 1]) - self.wire(writeAG.ports.restart, self.delayed_restarts[self.delay - 1]) + if self.use_default_addr: + self.wire(writeAG.ports.mux_sel, self.delayed_mux_sels[self.delay - 1]) + self.wire(writeAG.ports.restart, self.delayed_restarts[self.delay - 1]) # create accessor for edge newSG = SchedGen(iterator_support=edge["dim"], @@ -513,7 +532,8 @@ def get_delayed_write(self): def get_static_bitstream(self, config_path, in_file_name, - out_file_name): + out_file_name, + use_default_addr): input_ports = 1 output_ports = 1 @@ -524,6 +544,13 @@ def get_static_bitstream(self, tb2out0 = map_controller(extract_controller(config_path + '/' + out_file_name + '_2_tb2out_0.csv'), "tb2out0") tb2out1 = map_controller(extract_controller(config_path + '/' + out_file_name + '_2_tb2out_1.csv'), "tb2out1") + if not use_default_addr: + in2aggnt = map_controller(extract_controller(config_path + '/' + in_file_name + '_in2agg_0.csv'), "in2agg", use_default_addr) + agg2sramnt = map_controller(extract_controller(config_path + '/' + in_file_name + '_agg2sram.csv'), "agg2sram", use_default_addr) + sram2tbnt = map_controller(extract_controller(config_path + '/' + out_file_name + '_2_sram2tb.csv'), "sram2tb", use_default_addr) + tb2out0nt = map_controller(extract_controller(config_path + '/' + out_file_name + '_2_tb2out_0.csv'), "tb2out0", use_default_addr) + tb2out1nt = map_controller(extract_controller(config_path + '/' + out_file_name + '_2_tb2out_1.csv'), "tb2out1", use_default_addr) + # Getting bitstreams is a little unweildy due to fault (or its underlying implementation) not # handling arrays in the interface. # To alleviate this, we create the flattened wrapper so we can query widths of config @@ -596,36 +623,56 @@ def get_static_bitstream(self, for i in range(in2agg.dim): config.append((f"input_port0_2agg_forloop_ranges_{i}", in2agg.extent[i])) - config.append((f"input_port0_2agg_write_addr_gen_strides_{i}", in2agg.in_data_stride[i])) + config.append((f"input_port0_2agg_write_addr_gen_strides_{i}", in2aggnt.in_data_stride[i])) config.append((f"input_port0_2agg_write_sched_gen_sched_addr_gen_strides_{i}", in2agg.cyc_stride[i])) + if not use_default_addr: + config.append((f"input_port0_2agg_write_addr_gen_ranges_{i}", in2aggnt.extent[i])) + + if not use_default_addr: + config.append((f"input_port0_2agg_write_addr_gen_dimensionality", in2aggnt.dim)) + for i in range(agg2sram.dim): - config.append((f"agg_agg1_sram_edge_read_addr_gen_strides_{i}", agg2sram.out_data_stride[i])) + config.append((f"agg_agg1_sram_edge_read_addr_gen_strides_{i}", agg2sramnt.out_data_stride[i])) config.append((f"agg_agg1_sram_edge_forloop_ranges_{i}", agg2sram.extent[i])) - config.append((f"agg_agg1_sram_edge_write_addr_gen_strides_{i}", agg2sram.in_data_stride[i])) + config.append((f"agg_agg1_sram_edge_write_addr_gen_strides_{i}", agg2sramnt.in_data_stride[i])) config.append((f"agg_agg1_sram_edge_sched_gen_sched_addr_gen_strides_{i}", agg2sram.cyc_stride[i])) + if not use_default_addr: + config.append((f"agg_agg1_sram_edge_write_addr_gen_ranges_{i}", agg2sramnt.extent[i])) + tbs = [tb2out0, tb2out1] for i in range(sram2tb.dim): config.append((f"sram_tb_tb1_edge_forloop_ranges_{i}", sram2tb.extent[i])) - config.append((f"sram_tb_tb1_edge_read_addr_gen_strides_{i}", sram2tb.out_data_stride[i])) + config.append((f"sram_tb_tb1_edge_read_addr_gen_strides_{i}", sram2tbnt.out_data_stride[i])) config.append((f"sram_tb_tb1_edge_sched_gen_sched_addr_gen_strides_{i}", sram2tb.cyc_stride[i])) - config.append((f"sram_tb_tb1_edge_write_addr_gen_strides_{i}", sram2tb.in_data_stride[i])) + config.append((f"sram_tb_tb1_edge_write_addr_gen_strides_{i}", sram2tbnt.in_data_stride[i])) + + if not use_default_addr: + config.append((f"sram_tb_tb1_edge_read_addr_gen_ranges_{i}", sram2tbnt.extent[i])) tbs = [tb2out0, tb2out1] + tbsnt = [tb2out0nt, tb2out1nt] for tb in range(len(tbs)): elem = tbs[tb] + elemnt = tbsnt[tb] for i in range(elem.dim): if tb == 0: - config.append((f"tb2output_port0_read_addr_gen_strides_{i}", elem.out_data_stride[i])) + config.append((f"tb2output_port0_read_addr_gen_strides_{i}", elemnt.out_data_stride[i])) config.append((f"tb2output_port0_read_sched_gen_sched_addr_gen_strides_{i}", elem.cyc_stride[i])) config.append((f"tb2output_port0_forloop_ranges_{i}", elem.extent[i])) + + if not use_default_addr: + config.append((f"tb2output_port0_read_addr_gen_ranges_{i}", elemnt.extent[i])) else: - config.append((f"tb12output_port1_read_addr_gen_strides_{i}", elem.out_data_stride[i])) + config.append((f"tb12output_port1_read_addr_gen_strides_{i}", elemnt.out_data_stride[i])) config.append((f"tb12output_port1_read_sched_gen_sched_addr_gen_strides_{i}", elem.cyc_stride[i])) config.append((f"tb12output_port1_forloop_ranges_{i}", elem.extent[i])) + if not use_default_addr: + config.append((f"tb12output_port1_read_addr_gen_ranges_{i}", elemnt.extent[i])) + return trim_config_list(flattened, config) diff --git a/lake/utils/parse_clkwork_config.py b/lake/utils/parse_clkwork_config.py index 969ec870..1e9b8604 100644 --- a/lake/utils/parse_clkwork_config.py +++ b/lake/utils/parse_clkwork_config.py @@ -118,7 +118,7 @@ def extract_controller(file_path): return ctrl_info -def map_controller(controller, name): +def map_controller(controller, name, transform_data=True): ctrl_dim = controller.dim ctrl_ranges = controller.extent ctrl_cyc_strides = controller.cyc_stride @@ -148,15 +148,24 @@ def map_controller(controller, name): (tform_extent, tform_cyc_strides) = transform_strides_and_ranges(ctrl_ranges, ctrl_cyc_strides, ctrl_dim) tform_in_data_strides = None if ctrl_in_data_strt is not None: - (tform_extent, tform_in_data_strides) = transform_strides_and_ranges(ctrl_ranges, ctrl_in_data_strides, ctrl_dim) + if transform_data: + (tform_extent, tform_in_data_strides) = transform_strides_and_ranges(ctrl_ranges, ctrl_in_data_strides, ctrl_dim) + else: + tform_extent, tform_in_data_strides = ctrl_ranges, ctrl_in_data_strides tform_out_data_strides = None if ctrl_out_data_strt is not None: - (tform_extent, tform_out_data_strides) = transform_strides_and_ranges(ctrl_ranges, ctrl_out_data_strides, ctrl_dim) + if transform_data: + (tform_extent, tform_out_data_strides) = transform_strides_and_ranges(ctrl_ranges, ctrl_out_data_strides, ctrl_dim) + else: + tform_extent, tform_out_data_strides = ctrl_ranges, ctrl_out_data_strides tform_mux_data_strides = None if ctrl_mux_data_strt is not None: - (tform_extent, tform_mux_data_strides) = transform_strides_and_ranges(ctrl_ranges, ctrl_mux_data_strides, ctrl_dim) + if transform_data: + (tform_extent, tform_mux_data_strides) = transform_strides_and_ranges(ctrl_ranges, ctrl_mux_data_strides, ctrl_dim) + else: + tform_extent, tform_mux_data_strides = ctrl_ranges, ctrl_mux_data_strides # Basically give a starting margin for everything... garnet_delay = 0 diff --git a/tests/test_dsl_memtile.py b/tests/test_dsl_memtile.py index 7bdf2763..4aacdb38 100644 --- a/tests/test_dsl_memtile.py +++ b/tests/test_dsl_memtile.py @@ -23,9 +23,10 @@ def base_lake_tester(config_path, in_ports, out_ports, lt_dut, + use_default_addr=True, stencil_valid=False): - configs = lt_dut.get_static_bitstream(config_path, in_file_name, out_file_name) + configs = lt_dut.get_static_bitstream(config_path, in_file_name, out_file_name, use_default_addr) magma_dut = kts.util.to_magma(lt_dut, flatten_array=True, @@ -53,7 +54,8 @@ def gen_test_lake(config_path, out_file_name, in_ports, out_ports, - lt_dut) + lt_dut, + tile.addressor_info["use_default"]) tester.circuit.clk_en = 1 tester.circuit.clk_mem = 0 From 1e308383af9afc868f0f28f5444f4087f1e10001 Mon Sep 17 00:00:00 2001 From: Kavya Sreedhar Date: Sun, 10 Jan 2021 17:12:12 -0800 Subject: [PATCH 08/17] add dims for testing --- lake/dsl/hw_top_lake.py | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/lake/dsl/hw_top_lake.py b/lake/dsl/hw_top_lake.py index 22eebb57..5f76ca22 100644 --- a/lake/dsl/hw_top_lake.py +++ b/lake/dsl/hw_top_lake.py @@ -641,6 +641,9 @@ def get_static_bitstream(self, if not use_default_addr: config.append((f"agg_agg1_sram_edge_write_addr_gen_ranges_{i}", agg2sramnt.extent[i])) + if not use_default_addr: + config.append((f"agg_agg1_sram_edge_write_addr_gen_dimensionality", agg2sramnt.dim)) + tbs = [tb2out0, tb2out1] for i in range(sram2tb.dim): @@ -650,7 +653,12 @@ def get_static_bitstream(self, config.append((f"sram_tb_tb1_edge_write_addr_gen_strides_{i}", sram2tbnt.in_data_stride[i])) if not use_default_addr: - config.append((f"sram_tb_tb1_edge_read_addr_gen_ranges_{i}", sram2tbnt.extent[i])) + config.append((f"sram_tb_tb1_edge_write_addr_gen_ranges_{i}", sram2tbnt.extent[i])) + + if not use_default_addr: + config.append((f"sram_tb_tb1_edge_write_addr_gen_dimensionality", sram2tbnt.dim)) + config.append((f"tb2output_port0_read_addr_gen_dimensionality", tb2out0nt.dim)) + config.append((f"tb12output_port1_read_addr_gen_dimensionality", tb2out1nt.dim)) tbs = [tb2out0, tb2out1] tbsnt = [tb2out0nt, tb2out1nt] From 1c9012ebe1cc804f6e11deeb5ffa26335f455525 Mon Sep 17 00:00:00 2001 From: Kavya Sreedhar Date: Sun, 10 Jan 2021 17:27:33 -0800 Subject: [PATCH 09/17] add dims for testing --- lake/dsl/hw_top_lake.py | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/lake/dsl/hw_top_lake.py b/lake/dsl/hw_top_lake.py index 5f76ca22..9d72fbe6 100644 --- a/lake/dsl/hw_top_lake.py +++ b/lake/dsl/hw_top_lake.py @@ -640,9 +640,11 @@ def get_static_bitstream(self, if not use_default_addr: config.append((f"agg_agg1_sram_edge_write_addr_gen_ranges_{i}", agg2sramnt.extent[i])) + config.append((f"agg_agg1_sram_edge_read_addr_gen_ranges_{i}", agg2sramnt.extent[i])) if not use_default_addr: config.append((f"agg_agg1_sram_edge_write_addr_gen_dimensionality", agg2sramnt.dim)) + config.append((f"agg_agg1_sram_edge_read_addr_gen_dimensionality", agg2sramnt.dim)) tbs = [tb2out0, tb2out1] @@ -654,9 +656,11 @@ def get_static_bitstream(self, if not use_default_addr: config.append((f"sram_tb_tb1_edge_write_addr_gen_ranges_{i}", sram2tbnt.extent[i])) + config.append((f"sram_tb_tb1_edge_read_addr_gen_ranges_{i}", sram2tbnt.extent[i])) if not use_default_addr: config.append((f"sram_tb_tb1_edge_write_addr_gen_dimensionality", sram2tbnt.dim)) + config.append((f"sram_tb_tb1_edge_read_addr_gen_dimensionality", sram2tbnt.dim)) config.append((f"tb2output_port0_read_addr_gen_dimensionality", tb2out0nt.dim)) config.append((f"tb12output_port1_read_addr_gen_dimensionality", tb2out1nt.dim)) From 8f8180ba396495525d6059fa00283d679a6e2d37 Mon Sep 17 00:00:00 2001 From: Kavya Sreedhar Date: Sun, 10 Jan 2021 18:01:29 -0800 Subject: [PATCH 10/17] integration working, need to debug addr design --- lake/dsl/dsl_examples/memtile.py | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/lake/dsl/dsl_examples/memtile.py b/lake/dsl/dsl_examples/memtile.py index aecf3a4a..b1ae5aab 100644 --- a/lake/dsl/dsl_examples/memtile.py +++ b/lake/dsl/dsl_examples/memtile.py @@ -60,17 +60,17 @@ def create_og_design6(): offset = var_f("starting_addr") uc0 = scan_const_f(lambda z: if_f(eq_f(z, sub_f(r0, int_f(1))), int_f(0), add_f(z, int_f(1)))) - uc0 = scan_const_f(lambda z: if_f(eq_f(dim, int_f(0)), int_f(0), uc0.get_seq())) + #uc0 = scan_const_f(lambda z: if_f(eq_f(dim, int_f(0)), int_f(0), uc0.get_seq())) uc1 = scan_const_f(lambda z: if_f(eq_f(uc0.get_seq(), sub_f(r0, int_f(1))), add_f(z, int_f(1)), z)) - uc1 = scan_const_f(lambda z: if_f(eq_f(dim, int_f(1)), int_f(0), uc1.get_seq())) + #uc1 = scan_const_f(lambda z: if_f(eq_f(dim, int_f(1)), int_f(0), uc1.get_seq())) uc2 = scan_const_f(lambda z: if_f(eq_f(uc1.get_seq(), sub_f(r1, int_f(1))), add_f(z, int_f(1)), z)) - uc2 = scan_const_f(lambda z: if_f(eq_f(dim, int_f(2)), int_f(0), uc2.get_seq())) + #uc2 = scan_const_f(lambda z: if_f(eq_f(dim, int_f(2)), int_f(0), uc2.get_seq())) uc3 = scan_const_f(lambda z: if_f(eq_f(uc2.get_seq(), sub_f(r2, int_f(1))), add_f(z, int_f(1)), z)) - uc3 = scan_const_f(lambda z: if_f(eq_f(dim, int_f(3)), int_f(0), uc3.get_seq())) + #uc3 = scan_const_f(lambda z: if_f(eq_f(dim, int_f(3)), int_f(0), uc3.get_seq())) uc4 = scan_const_f(lambda z: if_f(eq_f(uc3.get_seq(), sub_f(r3, int_f(1))), add_f(z, int_f(1)), z)) - uc4 = scan_const_f(lambda z: if_f(eq_f(dim, int_f(4)), int_f(0), uc4.get_seq())) + #uc4 = scan_const_f(lambda z: if_f(eq_f(dim, int_f(4)), int_f(0), uc4.get_seq())) uc5 = scan_const_f(lambda z: if_f(eq_f(uc4.get_seq(), sub_f(r4, int_f(1))), add_f(z, int_f(1)), z)) - uc5 = scan_const_f(lambda z: if_f(eq_f(dim, int_f(5)), int_f(0), uc5.get_seq())) + #uc5 = scan_const_f(lambda z: if_f(eq_f(dim, int_f(5)), int_f(0), uc5.get_seq())) c0 = scan_const_f(lambda z: if_f(eq_f(uc0.get_seq(), sub_f(r0, int_f(1))), int_f(0), add_f(z, s0))) c1 = scan_const_f(lambda z: if_f(eq_f(uc0.get_seq(), sub_f(r0, int_f(1))), add_f(z, s1), z)) From e73c64740eab10b049b75e0fc23f92d6685e2299 Mon Sep 17 00:00:00 2001 From: Kavya Sreedhar Date: Sun, 10 Jan 2021 18:16:55 -0800 Subject: [PATCH 11/17] comment out tempdir, trace for push --- lake/dsl/dsl_examples/memtile.py | 2 +- tests/test_dsl_memtile.py | 5 +++-- 2 files changed, 4 insertions(+), 3 deletions(-) diff --git a/lake/dsl/dsl_examples/memtile.py b/lake/dsl/dsl_examples/memtile.py index b1ae5aab..94c67c49 100644 --- a/lake/dsl/dsl_examples/memtile.py +++ b/lake/dsl/dsl_examples/memtile.py @@ -82,7 +82,7 @@ def create_og_design6(): return scan_const_f(lambda z: add_f(offset, add_f(c0.get_seq(), add_f(c1.get_seq(), add_f(c2.get_seq(), add_f(c3.get_seq(), add_f(c4.get_seq(), c5.get_seq()))))))) og_design6 = create_og_design6() -tile.set_addressor(og_design6, "og_design6") +# tile.set_addressor(og_design6, "og_design6") # for both compiler collateral and HW generation # tile.construct_lake("memtile.sv") diff --git a/tests/test_dsl_memtile.py b/tests/test_dsl_memtile.py index 4aacdb38..37f1836c 100644 --- a/tests/test_dsl_memtile.py +++ b/tests/test_dsl_memtile.py @@ -88,14 +88,15 @@ def gen_test_lake(config_path, tester.step(2) with tempfile.TemporaryDirectory() as tempdir: - tempdir = "hw" + # tempdir = "hw" if not tile.addressor_info["use_default"]: addr_verilog = tile.addressor_info["name"] + ".v" tile.print_verilog_helper(addr_verilog, "w+", True) shutil.copy(addr_verilog, tempdir) tester.compile_and_run(target="verilator", directory=tempdir, - flags=["-Wno-fatal", "--trace"]) + flags=["-Wno-fatal"]) + # flags=["-Wno-fatal", "--trace"]) def test_conv_3_3(): From 4f7c373ad9e7d3b27e4247f0aa58d3f6f44a3225 Mon Sep 17 00:00:00 2001 From: Kavya Sreedhar Date: Sun, 10 Jan 2021 19:36:21 -0800 Subject: [PATCH 12/17] pycodestyle --- lake/dsl/dsl_examples/memtile.py | 14 +++++++----- lake/dsl/hw_top_lake.py | 38 ++++++++++++++++---------------- lake/dsl/top_lake.py | 10 ++++----- 3 files changed, 32 insertions(+), 30 deletions(-) diff --git a/lake/dsl/dsl_examples/memtile.py b/lake/dsl/dsl_examples/memtile.py index 94c67c49..501775c3 100644 --- a/lake/dsl/dsl_examples/memtile.py +++ b/lake/dsl/dsl_examples/memtile.py @@ -51,6 +51,7 @@ # addressor in frail # original addressor design + def create_og_design6(): # configuration registers @@ -60,17 +61,17 @@ def create_og_design6(): offset = var_f("starting_addr") uc0 = scan_const_f(lambda z: if_f(eq_f(z, sub_f(r0, int_f(1))), int_f(0), add_f(z, int_f(1)))) - #uc0 = scan_const_f(lambda z: if_f(eq_f(dim, int_f(0)), int_f(0), uc0.get_seq())) + # uc0 = scan_const_f(lambda z: if_f(eq_f(dim, int_f(0)), int_f(0), uc0.get_seq())) uc1 = scan_const_f(lambda z: if_f(eq_f(uc0.get_seq(), sub_f(r0, int_f(1))), add_f(z, int_f(1)), z)) - #uc1 = scan_const_f(lambda z: if_f(eq_f(dim, int_f(1)), int_f(0), uc1.get_seq())) + # uc1 = scan_const_f(lambda z: if_f(eq_f(dim, int_f(1)), int_f(0), uc1.get_seq())) uc2 = scan_const_f(lambda z: if_f(eq_f(uc1.get_seq(), sub_f(r1, int_f(1))), add_f(z, int_f(1)), z)) - #uc2 = scan_const_f(lambda z: if_f(eq_f(dim, int_f(2)), int_f(0), uc2.get_seq())) + # uc2 = scan_const_f(lambda z: if_f(eq_f(dim, int_f(2)), int_f(0), uc2.get_seq())) uc3 = scan_const_f(lambda z: if_f(eq_f(uc2.get_seq(), sub_f(r2, int_f(1))), add_f(z, int_f(1)), z)) - #uc3 = scan_const_f(lambda z: if_f(eq_f(dim, int_f(3)), int_f(0), uc3.get_seq())) + # uc3 = scan_const_f(lambda z: if_f(eq_f(dim, int_f(3)), int_f(0), uc3.get_seq())) uc4 = scan_const_f(lambda z: if_f(eq_f(uc3.get_seq(), sub_f(r3, int_f(1))), add_f(z, int_f(1)), z)) - #uc4 = scan_const_f(lambda z: if_f(eq_f(dim, int_f(4)), int_f(0), uc4.get_seq())) + # uc4 = scan_const_f(lambda z: if_f(eq_f(dim, int_f(4)), int_f(0), uc4.get_seq())) uc5 = scan_const_f(lambda z: if_f(eq_f(uc4.get_seq(), sub_f(r4, int_f(1))), add_f(z, int_f(1)), z)) - #uc5 = scan_const_f(lambda z: if_f(eq_f(dim, int_f(5)), int_f(0), uc5.get_seq())) + # uc5 = scan_const_f(lambda z: if_f(eq_f(dim, int_f(5)), int_f(0), uc5.get_seq())) c0 = scan_const_f(lambda z: if_f(eq_f(uc0.get_seq(), sub_f(r0, int_f(1))), int_f(0), add_f(z, s0))) c1 = scan_const_f(lambda z: if_f(eq_f(uc0.get_seq(), sub_f(r0, int_f(1))), add_f(z, s1), z)) @@ -81,6 +82,7 @@ def create_og_design6(): return scan_const_f(lambda z: add_f(offset, add_f(c0.get_seq(), add_f(c1.get_seq(), add_f(c2.get_seq(), add_f(c3.get_seq(), add_f(c4.get_seq(), c5.get_seq()))))))) + og_design6 = create_og_design6() # tile.set_addressor(og_design6, "og_design6") diff --git a/lake/dsl/hw_top_lake.py b/lake/dsl/hw_top_lake.py index 9d72fbe6..d75c89ba 100644 --- a/lake/dsl/hw_top_lake.py +++ b/lake/dsl/hw_top_lake.py @@ -263,12 +263,12 @@ def increment_cycle_count(self): newAG = AddrGen(iterator_support=output_dim, config_width=max(1, clog2(output_stride))) # self.default_config_width) self.add_child(f"{out_mem}2output_port{output_port_index}_read_addr_gen", - newAG, - clk=self.gclk, - rst_n=self.rst_n, - step=self.valid, - mux_sel=forloop.ports.mux_sel_out, - restart=forloop.ports.restart) + newAG, + clk=self.gclk, + rst_n=self.rst_n, + step=self.valid, + mux_sel=forloop.ports.mux_sel_out, + restart=forloop.ports.restart) else: newAG = AddressorWrapper(self.addressor_name) @@ -276,7 +276,7 @@ def increment_cycle_count(self): newAG, clk=self.gclk, step=self.valid) - + if self.memories[out_mem]["num_read_write_ports"] == 0: safe_wire(self, self.mem_insts[out_mem].ports.read_addr[0], newAG.ports.addr_out) else: @@ -322,14 +322,14 @@ def increment_cycle_count(self): # create input addressor if self.use_default_addr: readAG = AddrGen(iterator_support=edge["dim"], - config_width=self.default_config_width) + config_width=self.default_config_width) self.add_child(f"{edge_name}_read_addr_gen", - readAG, - clk=self.gclk, - rst_n=self.rst_n, - step=self.valid, - mux_sel=forloop.ports.mux_sel_out, - restart=forloop.ports.restart) + readAG, + clk=self.gclk, + rst_n=self.rst_n, + step=self.valid, + mux_sel=forloop.ports.mux_sel_out, + restart=forloop.ports.restart) else: readAG = AddressorWrapper(self.addressor_name) self.add_child(f"{edge_name}_read_addr_gen", @@ -384,12 +384,12 @@ def increment_cycle_count(self): # create output addressor if self.use_default_addr: writeAG = AddrGen(iterator_support=edge["dim"], - config_width=self.default_config_width) + config_width=self.default_config_width) # step, mux_sel, restart may need delayed signals (assigned later) self.add_child(f"{edge_name}_write_addr_gen", - writeAG, - clk=self.gclk, - rst_n=self.rst_n) + writeAG, + clk=self.gclk, + rst_n=self.rst_n) else: writeAG = AddressorWrapper(self.addressor_name) self.add_child(f"{edge_name}_write_addr_gen", @@ -628,7 +628,7 @@ def get_static_bitstream(self, if not use_default_addr: config.append((f"input_port0_2agg_write_addr_gen_ranges_{i}", in2aggnt.extent[i])) - + if not use_default_addr: config.append((f"input_port0_2agg_write_addr_gen_dimensionality", in2aggnt.dim)) diff --git a/lake/dsl/top_lake.py b/lake/dsl/top_lake.py index a45d7e5f..b3aedf4b 100644 --- a/lake/dsl/top_lake.py +++ b/lake/dsl/top_lake.py @@ -317,7 +317,7 @@ def construct_lake(self, filename="Lake_hw.sv", wrap_cfg=False): optimize_if=False, check_flip_flop_always_ff=False, additional_passes={"change sram port names": sram_port_pass}) - + if not self.addressor_info["use_default"]: self.print_verilog_helper(filename, "a", True) @@ -326,7 +326,7 @@ def print_verilog_helper(self, filename, mode, get_verilog): orig_stdout = sys.stdout sys.stdout = fi print_verilog(self.addressor_info["addressor"], - top_name=self.addressor_info["name"], - add_step=True, - get_verilog=get_verilog) - sys.stdout = orig_stdout \ No newline at end of file + top_name=self.addressor_info["name"], + add_step=True, + get_verilog=get_verilog) + sys.stdout = orig_stdout From 79106f8eee303dd719475f3c896a4ac86f1afebe Mon Sep 17 00:00:00 2001 From: Kavya Sreedhar Date: Sun, 10 Jan 2021 19:41:54 -0800 Subject: [PATCH 13/17] pycodestyle --- tests/test_dsl_memtile.py | 1 - 1 file changed, 1 deletion(-) diff --git a/tests/test_dsl_memtile.py b/tests/test_dsl_memtile.py index 37f1836c..3836f409 100644 --- a/tests/test_dsl_memtile.py +++ b/tests/test_dsl_memtile.py @@ -96,7 +96,6 @@ def gen_test_lake(config_path, tester.compile_and_run(target="verilator", directory=tempdir, flags=["-Wno-fatal"]) - # flags=["-Wno-fatal", "--trace"]) def test_conv_3_3(): From f908006a8c44f7ce9853d700ec511c5458dd302f Mon Sep 17 00:00:00 2001 From: Kavya Sreedhar Date: Sun, 10 Jan 2021 20:01:45 -0800 Subject: [PATCH 14/17] move testing of frail addressors to Lake so that frail can be included in lake --- tests/test_frail.py | 106 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 106 insertions(+) create mode 100644 tests/test_frail.py diff --git a/tests/test_frail.py b/tests/test_frail.py new file mode 100644 index 00000000..aa9ce0f3 --- /dev/null +++ b/tests/test_frail.py @@ -0,0 +1,106 @@ +import magma as m +import fault +import time +import tempfile +import shutil +import os +import pathlib +import pytest +import random + +from lake.models.addr_gen_model import AddrGenModel +from lake.utils.util import transform_strides_and_ranges + + +@pytest.mark.parametrize("test_rand", [False, True]) +@pytest.mark.parametrize("design", ["og_design", "op_design"]) +def test_addr_design( + test_rand, + design, + starting_addr=0, + strides_0=15, + strides_1=13, + ranges_0=2, + ranges_1=13): + + if test_rand: + max_value = 2**5 + starting_addr = random.randint(0, max_value - 1) + strides_0 = random.randint(0, max_value - 1) + strides_1 = random.randint(0, max_value - 1) + ranges_0 = random.randint(0, max_value - 1) + ranges_1 = random.randint(0, max_value - 1) + + print(starting_addr, strides_0, strides_1, ranges_0, ranges_1) + + # set up addressor model + model_ag = AddrGenModel(2, 16) + + config = {} + config["starting_addr"] = starting_addr + config["dimensionality"] = 2 + config["strides_0"] = strides_0 + config["strides_1"] = strides_1 + config["ranges_0"] = ranges_0 + config["ranges_1"] = ranges_1 + + model_ag.set_config(config) + + # set up frail design with Verilog + frail_dir = pathlib.Path(__file__).parent.parent.absolute() + + # get Magma circuit from Verilog + dut = m.define_from_verilog_file( + f"{frail_dir}/verilog/{design}.v", + target_modules=[design], + type_map={ + "clk": m.In( + m.Clock)})[0] + print(f"Imported as magma circuit: {dut}") + + tester = fault.Tester(dut, dut.clk) + + # no need to rst_n or clk_en yet + + # config regs + if design == "design_b" or design == "op_design": + tranges, tstrides = transform_strides_and_ranges( + [ranges_0, ranges_1], + [strides_0, strides_1], + 2) + tester.circuit.x_max = ranges_0 #tranges[0] + tester.circuit.x_stride = tstrides[0] + tester.circuit.y_max = ranges_1 #tranges[1] + tester.circuit.y_stride = tstrides[1] + tester.circuit.offset = starting_addr + print("transformed:", tranges, tstrides) + else: + tester.circuit.x_max = ranges_0 + tester.circuit.x_stride = strides_0 + tester.circuit.y_max = ranges_1 + tester.circuit.y_stride = strides_1 + tester.circuit.offset = starting_addr + + tester.circuit.step = 1 + + for i in range(min(1000, ranges_0 * ranges_1 - 1)): + # start with first addr on rising clk edge + tester.circuit.clk = 1 + tester.step(2) + tester.eval() + model_ag.step() + tester.circuit.addr_out.expect(model_ag.get_address()) + # print(model_ag.get_address()) + + with tempfile.TemporaryDirectory() as tempdir: + # tempdir = design + shutil.copy(f"{frail_dir}/verilog/{design}.v", tempdir) + tester.compile_and_run(target="verilator", + directory=tempdir, + skip_compile=True, + flags=["-Wno-fatal"]) + # flags=["-Wno-fatal", "--trace"]) + + +if __name__ == "__main__": + test_addr_design(True, "op_design")#, 0, 15, 20, 12, 15) From bacafb92241a414703e560f713cbf39ca336b3d8 Mon Sep 17 00:00:00 2001 From: Kavya Sreedhar Date: Sun, 10 Jan 2021 22:58:31 -0800 Subject: [PATCH 15/17] add frail to setup --- setup.py | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/setup.py b/setup.py index 79461444..917606e3 100644 --- a/setup.py +++ b/setup.py @@ -30,6 +30,7 @@ "kratos", "fault", "magma-lang", - "pytest" + "pytest", + "frail" ] ) From b05542ab561d56db94f2df082a8408c7b9d8d403 Mon Sep 17 00:00:00 2001 From: Kavya Sreedhar Date: Fri, 15 Jan 2021 13:44:09 -0800 Subject: [PATCH 16/17] cleanup --- lake/dsl/dsl_examples/memtile.py | 38 ---------------------- lake/dsl/hw_top_lake.py | 56 +++++--------------------------- tests/test_dsl_memtile.py | 2 +- 3 files changed, 9 insertions(+), 87 deletions(-) diff --git a/lake/dsl/dsl_examples/memtile.py b/lake/dsl/dsl_examples/memtile.py index 501775c3..88a998ce 100644 --- a/lake/dsl/dsl_examples/memtile.py +++ b/lake/dsl/dsl_examples/memtile.py @@ -48,43 +48,5 @@ tile.add_edge("sram", "tb") tile.add_edge("sram", "tb1") -# addressor in frail -# original addressor design - - -def create_og_design6(): - - # configuration registers - r0, r1, r2, r3, r4, r5 = var_f("ranges_0"), var_f("ranges_1"), var_f("ranges_2"), var_f("ranges_3"), var_f("ranges_4"), var_f("ranges_5") - s0, s1, s2, s3, s4, s5 = var_f("strides_0"), var_f("strides_1"), var_f("strides_2"), var_f("strides_3"), var_f("strides_4"), var_f("strides_5") - dim = var_f("dimensionality") - offset = var_f("starting_addr") - - uc0 = scan_const_f(lambda z: if_f(eq_f(z, sub_f(r0, int_f(1))), int_f(0), add_f(z, int_f(1)))) - # uc0 = scan_const_f(lambda z: if_f(eq_f(dim, int_f(0)), int_f(0), uc0.get_seq())) - uc1 = scan_const_f(lambda z: if_f(eq_f(uc0.get_seq(), sub_f(r0, int_f(1))), add_f(z, int_f(1)), z)) - # uc1 = scan_const_f(lambda z: if_f(eq_f(dim, int_f(1)), int_f(0), uc1.get_seq())) - uc2 = scan_const_f(lambda z: if_f(eq_f(uc1.get_seq(), sub_f(r1, int_f(1))), add_f(z, int_f(1)), z)) - # uc2 = scan_const_f(lambda z: if_f(eq_f(dim, int_f(2)), int_f(0), uc2.get_seq())) - uc3 = scan_const_f(lambda z: if_f(eq_f(uc2.get_seq(), sub_f(r2, int_f(1))), add_f(z, int_f(1)), z)) - # uc3 = scan_const_f(lambda z: if_f(eq_f(dim, int_f(3)), int_f(0), uc3.get_seq())) - uc4 = scan_const_f(lambda z: if_f(eq_f(uc3.get_seq(), sub_f(r3, int_f(1))), add_f(z, int_f(1)), z)) - # uc4 = scan_const_f(lambda z: if_f(eq_f(dim, int_f(4)), int_f(0), uc4.get_seq())) - uc5 = scan_const_f(lambda z: if_f(eq_f(uc4.get_seq(), sub_f(r4, int_f(1))), add_f(z, int_f(1)), z)) - # uc5 = scan_const_f(lambda z: if_f(eq_f(dim, int_f(5)), int_f(0), uc5.get_seq())) - - c0 = scan_const_f(lambda z: if_f(eq_f(uc0.get_seq(), sub_f(r0, int_f(1))), int_f(0), add_f(z, s0))) - c1 = scan_const_f(lambda z: if_f(eq_f(uc0.get_seq(), sub_f(r0, int_f(1))), add_f(z, s1), z)) - c2 = scan_const_f(lambda z: if_f(eq_f(uc1.get_seq(), sub_f(r1, int_f(1))), add_f(z, s2), z)) - c3 = scan_const_f(lambda z: if_f(eq_f(uc2.get_seq(), sub_f(r2, int_f(1))), add_f(z, s3), z)) - c4 = scan_const_f(lambda z: if_f(eq_f(uc3.get_seq(), sub_f(r3, int_f(1))), add_f(z, s4), z)) - c5 = scan_const_f(lambda z: if_f(eq_f(uc4.get_seq(), sub_f(r4, int_f(1))), add_f(z, s5), z)) - - return scan_const_f(lambda z: add_f(offset, add_f(c0.get_seq(), add_f(c1.get_seq(), add_f(c2.get_seq(), add_f(c3.get_seq(), add_f(c4.get_seq(), c5.get_seq()))))))) - - -og_design6 = create_og_design6() -# tile.set_addressor(og_design6, "og_design6") - # for both compiler collateral and HW generation # tile.construct_lake("memtile.sv") diff --git a/lake/dsl/hw_top_lake.py b/lake/dsl/hw_top_lake.py index d75c89ba..07277906 100644 --- a/lake/dsl/hw_top_lake.py +++ b/lake/dsl/hw_top_lake.py @@ -532,8 +532,7 @@ def get_delayed_write(self): def get_static_bitstream(self, config_path, in_file_name, - out_file_name, - use_default_addr): + out_file_name): input_ports = 1 output_ports = 1 @@ -544,13 +543,6 @@ def get_static_bitstream(self, tb2out0 = map_controller(extract_controller(config_path + '/' + out_file_name + '_2_tb2out_0.csv'), "tb2out0") tb2out1 = map_controller(extract_controller(config_path + '/' + out_file_name + '_2_tb2out_1.csv'), "tb2out1") - if not use_default_addr: - in2aggnt = map_controller(extract_controller(config_path + '/' + in_file_name + '_in2agg_0.csv'), "in2agg", use_default_addr) - agg2sramnt = map_controller(extract_controller(config_path + '/' + in_file_name + '_agg2sram.csv'), "agg2sram", use_default_addr) - sram2tbnt = map_controller(extract_controller(config_path + '/' + out_file_name + '_2_sram2tb.csv'), "sram2tb", use_default_addr) - tb2out0nt = map_controller(extract_controller(config_path + '/' + out_file_name + '_2_tb2out_0.csv'), "tb2out0", use_default_addr) - tb2out1nt = map_controller(extract_controller(config_path + '/' + out_file_name + '_2_tb2out_1.csv'), "tb2out1", use_default_addr) - # Getting bitstreams is a little unweildy due to fault (or its underlying implementation) not # handling arrays in the interface. # To alleviate this, we create the flattened wrapper so we can query widths of config @@ -623,68 +615,36 @@ def get_static_bitstream(self, for i in range(in2agg.dim): config.append((f"input_port0_2agg_forloop_ranges_{i}", in2agg.extent[i])) - config.append((f"input_port0_2agg_write_addr_gen_strides_{i}", in2aggnt.in_data_stride[i])) + config.append((f"input_port0_2agg_write_addr_gen_strides_{i}", in2agg.in_data_stride[i])) config.append((f"input_port0_2agg_write_sched_gen_sched_addr_gen_strides_{i}", in2agg.cyc_stride[i])) - if not use_default_addr: - config.append((f"input_port0_2agg_write_addr_gen_ranges_{i}", in2aggnt.extent[i])) - - if not use_default_addr: - config.append((f"input_port0_2agg_write_addr_gen_dimensionality", in2aggnt.dim)) - for i in range(agg2sram.dim): - config.append((f"agg_agg1_sram_edge_read_addr_gen_strides_{i}", agg2sramnt.out_data_stride[i])) + config.append((f"agg_agg1_sram_edge_read_addr_gen_strides_{i}", agg2sram.out_data_stride[i])) config.append((f"agg_agg1_sram_edge_forloop_ranges_{i}", agg2sram.extent[i])) - config.append((f"agg_agg1_sram_edge_write_addr_gen_strides_{i}", agg2sramnt.in_data_stride[i])) + config.append((f"agg_agg1_sram_edge_write_addr_gen_strides_{i}", agg2sram.in_data_stride[i])) config.append((f"agg_agg1_sram_edge_sched_gen_sched_addr_gen_strides_{i}", agg2sram.cyc_stride[i])) - if not use_default_addr: - config.append((f"agg_agg1_sram_edge_write_addr_gen_ranges_{i}", agg2sramnt.extent[i])) - config.append((f"agg_agg1_sram_edge_read_addr_gen_ranges_{i}", agg2sramnt.extent[i])) - - if not use_default_addr: - config.append((f"agg_agg1_sram_edge_write_addr_gen_dimensionality", agg2sramnt.dim)) - config.append((f"agg_agg1_sram_edge_read_addr_gen_dimensionality", agg2sramnt.dim)) - tbs = [tb2out0, tb2out1] for i in range(sram2tb.dim): config.append((f"sram_tb_tb1_edge_forloop_ranges_{i}", sram2tb.extent[i])) - config.append((f"sram_tb_tb1_edge_read_addr_gen_strides_{i}", sram2tbnt.out_data_stride[i])) + config.append((f"sram_tb_tb1_edge_read_addr_gen_strides_{i}", sram2tb.out_data_stride[i])) config.append((f"sram_tb_tb1_edge_sched_gen_sched_addr_gen_strides_{i}", sram2tb.cyc_stride[i])) - config.append((f"sram_tb_tb1_edge_write_addr_gen_strides_{i}", sram2tbnt.in_data_stride[i])) - - if not use_default_addr: - config.append((f"sram_tb_tb1_edge_write_addr_gen_ranges_{i}", sram2tbnt.extent[i])) - config.append((f"sram_tb_tb1_edge_read_addr_gen_ranges_{i}", sram2tbnt.extent[i])) - - if not use_default_addr: - config.append((f"sram_tb_tb1_edge_write_addr_gen_dimensionality", sram2tbnt.dim)) - config.append((f"sram_tb_tb1_edge_read_addr_gen_dimensionality", sram2tbnt.dim)) - config.append((f"tb2output_port0_read_addr_gen_dimensionality", tb2out0nt.dim)) - config.append((f"tb12output_port1_read_addr_gen_dimensionality", tb2out1nt.dim)) + config.append((f"sram_tb_tb1_edge_write_addr_gen_strides_{i}", sram2tb.in_data_stride[i])) tbs = [tb2out0, tb2out1] - tbsnt = [tb2out0nt, tb2out1nt] for tb in range(len(tbs)): elem = tbs[tb] - elemnt = tbsnt[tb] for i in range(elem.dim): if tb == 0: - config.append((f"tb2output_port0_read_addr_gen_strides_{i}", elemnt.out_data_stride[i])) + config.append((f"tb2output_port0_read_addr_gen_strides_{i}", elem.out_data_stride[i])) config.append((f"tb2output_port0_read_sched_gen_sched_addr_gen_strides_{i}", elem.cyc_stride[i])) config.append((f"tb2output_port0_forloop_ranges_{i}", elem.extent[i])) - - if not use_default_addr: - config.append((f"tb2output_port0_read_addr_gen_ranges_{i}", elemnt.extent[i])) else: - config.append((f"tb12output_port1_read_addr_gen_strides_{i}", elemnt.out_data_stride[i])) + config.append((f"tb12output_port1_read_addr_gen_strides_{i}", elem.out_data_stride[i])) config.append((f"tb12output_port1_read_sched_gen_sched_addr_gen_strides_{i}", elem.cyc_stride[i])) config.append((f"tb12output_port1_forloop_ranges_{i}", elem.extent[i])) - if not use_default_addr: - config.append((f"tb12output_port1_read_addr_gen_ranges_{i}", elemnt.extent[i])) - return trim_config_list(flattened, config) diff --git a/tests/test_dsl_memtile.py b/tests/test_dsl_memtile.py index 3836f409..12facab8 100644 --- a/tests/test_dsl_memtile.py +++ b/tests/test_dsl_memtile.py @@ -26,7 +26,7 @@ def base_lake_tester(config_path, use_default_addr=True, stencil_valid=False): - configs = lt_dut.get_static_bitstream(config_path, in_file_name, out_file_name, use_default_addr) + configs = lt_dut.get_static_bitstream(config_path, in_file_name, out_file_name) magma_dut = kts.util.to_magma(lt_dut, flatten_array=True, From 65d15bd81c86db45a5244584d6d871dca095ce15 Mon Sep 17 00:00:00 2001 From: Kavya Sreedhar Date: Fri, 15 Jan 2021 13:45:04 -0800 Subject: [PATCH 17/17] delete testing file --- tests/test_frail.py | 106 -------------------------------------------- 1 file changed, 106 deletions(-) delete mode 100644 tests/test_frail.py diff --git a/tests/test_frail.py b/tests/test_frail.py deleted file mode 100644 index aa9ce0f3..00000000 --- a/tests/test_frail.py +++ /dev/null @@ -1,106 +0,0 @@ -import magma as m -import fault -import time -import tempfile -import shutil -import os -import pathlib -import pytest -import random - -from lake.models.addr_gen_model import AddrGenModel -from lake.utils.util import transform_strides_and_ranges - - -@pytest.mark.parametrize("test_rand", [False, True]) -@pytest.mark.parametrize("design", ["og_design", "op_design"]) -def test_addr_design( - test_rand, - design, - starting_addr=0, - strides_0=15, - strides_1=13, - ranges_0=2, - ranges_1=13): - - if test_rand: - max_value = 2**5 - starting_addr = random.randint(0, max_value - 1) - strides_0 = random.randint(0, max_value - 1) - strides_1 = random.randint(0, max_value - 1) - ranges_0 = random.randint(0, max_value - 1) - ranges_1 = random.randint(0, max_value - 1) - - print(starting_addr, strides_0, strides_1, ranges_0, ranges_1) - - # set up addressor model - model_ag = AddrGenModel(2, 16) - - config = {} - config["starting_addr"] = starting_addr - config["dimensionality"] = 2 - config["strides_0"] = strides_0 - config["strides_1"] = strides_1 - config["ranges_0"] = ranges_0 - config["ranges_1"] = ranges_1 - - model_ag.set_config(config) - - # set up frail design with Verilog - frail_dir = pathlib.Path(__file__).parent.parent.absolute() - - # get Magma circuit from Verilog - dut = m.define_from_verilog_file( - f"{frail_dir}/verilog/{design}.v", - target_modules=[design], - type_map={ - "clk": m.In( - m.Clock)})[0] - print(f"Imported as magma circuit: {dut}") - - tester = fault.Tester(dut, dut.clk) - - # no need to rst_n or clk_en yet - - # config regs - if design == "design_b" or design == "op_design": - tranges, tstrides = transform_strides_and_ranges( - [ranges_0, ranges_1], - [strides_0, strides_1], - 2) - tester.circuit.x_max = ranges_0 #tranges[0] - tester.circuit.x_stride = tstrides[0] - tester.circuit.y_max = ranges_1 #tranges[1] - tester.circuit.y_stride = tstrides[1] - tester.circuit.offset = starting_addr - print("transformed:", tranges, tstrides) - else: - tester.circuit.x_max = ranges_0 - tester.circuit.x_stride = strides_0 - tester.circuit.y_max = ranges_1 - tester.circuit.y_stride = strides_1 - tester.circuit.offset = starting_addr - - tester.circuit.step = 1 - - for i in range(min(1000, ranges_0 * ranges_1 - 1)): - # start with first addr on rising clk edge - tester.circuit.clk = 1 - tester.step(2) - tester.eval() - model_ag.step() - tester.circuit.addr_out.expect(model_ag.get_address()) - # print(model_ag.get_address()) - - with tempfile.TemporaryDirectory() as tempdir: - # tempdir = design - shutil.copy(f"{frail_dir}/verilog/{design}.v", tempdir) - tester.compile_and_run(target="verilator", - directory=tempdir, - skip_compile=True, - flags=["-Wno-fatal"]) - # flags=["-Wno-fatal", "--trace"]) - - -if __name__ == "__main__": - test_addr_design(True, "op_design")#, 0, 15, 20, 12, 15)