From d7e095b5a644cbe44dcb7b9bf426936bf8ba6b8a Mon Sep 17 00:00:00 2001
From: Ovidiu Sas <osas@voipembedded.com>
Date: Fri, 15 May 2026 00:50:39 -0400
Subject: [PATCH] core: implement FAST_LOCK for aarch64

---
 Makefile.defs | 6 +++++-
 fastlock.h    | 8 ++++++++
 futex_lock.h  | 3 +++
 3 files changed, 16 insertions(+), 1 deletion(-)

diff --git a/Makefile.defs b/Makefile.defs
index 629adadc844..095399f60e2 100644
--- a/Makefile.defs
+++ b/Makefile.defs
@@ -230,7 +230,7 @@ arm_macros= __arm__ __thumb__
 arm6_macros= __ARM_ARCH_6__
 arm7_macros= __ARM_ARCH_7__ __ARM_ARCH_7A__
 
-arm64_macros= __AARCH64EL__
+arm64_macros= __aarch64__ __AARCH64EL__ __AARCH64EB__
 
 ppc_macros= __powerpc __powerpc__ __POWERPC__ __ppc__ _ARCH_PPC
 ppc64_macros= __ppc64__ _ARCH_PPC64
@@ -752,6 +752,10 @@ ifeq ($(ARCH), arm7)
 	use_fast_lock=yes
 endif
 
+ifeq ($(ARCH), aarch64)
+	use_fast_lock=yes
+endif
+
 ifeq ($(ARCH), ppc)
 	use_fast_lock=yes
 endif
diff --git a/fastlock.h b/fastlock.h
index 442864aa290..35b0ef5cdc3 100644
--- a/fastlock.h
+++ b/fastlock.h
@@ -147,6 +147,12 @@ inline static int tsl(volatile int* lock)
 #endif
 			: "=&r" (val) : "r"(1), "r" (lock) : "cc", "memory"
 	);
+#elif defined(__CPU_aarch64)
+#ifdef SPIN_OPTIMIZE
+	if (__atomic_load_n(lock, __ATOMIC_RELAXED))
+		return 1;
+#endif
+	val = __atomic_exchange_n(lock, 1, __ATOMIC_ACQUIRE);
 #elif defined(__CPU_ppc) || defined(__CPU_ppc64)
 	asm volatile(
 			"1: lwarx  %0, 0, %2\n\t"
@@ -300,6 +306,8 @@ inline static void release_lock(fl_lock_t* lock_struct)
 		" str %1, [%2] \n\r"
 		: "=m"(*lock) : "r"(0), "r"(lock) : "memory"
 	);
+#elif defined(__CPU_aarch64)
+	__atomic_store_n(lock, 0, __ATOMIC_RELEASE);
 #elif defined(__CPU_ppc) || defined(__CPU_ppc64)
 	asm volatile(
 			/* "sync\n\t"  lwsync is faster and will work
diff --git a/futex_lock.h b/futex_lock.h
index 2e859b0fdc2..5e0d0bbebdc 100644
--- a/futex_lock.h
+++ b/futex_lock.h
@@ -159,6 +159,9 @@ inline static int _atomic_xchg(volatile int *lock, int newval)
 			: "r"(newval), "r" (lock) : "memory"
 	);
 
+#elif defined(__CPU_aarch64)
+	val = __atomic_exchange_n(lock, newval, __ATOMIC_ACQ_REL);
+
 #elif defined(__CPU_ppc) || defined(__CPU_ppc64)
 	asm volatile(
 			"1: lwarx  %0, 0, %2\n\t"