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MIPI: combo_dev_attr_t built with raw_data_type=0 / wrong enIntfMode; ignored .ini values (cv200 / OV2735) #278

@moontwister

Description

@moontwister

Summary

On hisilicon-hi3516cv200 (verified on Hi3518EV200 + OV2735, 2-lane MIPI RAW10), majestic appears to skip the sensor .ini's [mipi] section when building the kernel ioctls that configure the MIPI receiver block. Two ioctls land with wrong / uninitialized values, no frames flow, and majestic logs the familiar Timeout from venc channel 0 / ERR_ISP_? cascade.

Symptom

  • /proc/driver/hi_mipi stays at boot defaults (LaneNum=4, PhyMode=CMOS, DataType=N/A) instead of the sensor's LaneNum=2 RAW10 MIPI — i.e. the MIPI RX block is never actually configured.
  • ISP IRQ count = 0, VI IntCnt = 0, no frames reach VENC.
  • Vendor firmware on the same hardware produces LaneNum=2 / RAW10 / MIPI (confirmed via a vendor-FW round-trip flash and snapshot diff).

Root cause (two ioctls)

After tracing with an LD_PRELOAD shim around ioctl() (source attached below), majestic's calls to two ioctls arrive with wrong values:

1. HI_MIPI_SET_DEV_ATTR (ioctl 0x41306d01, _IOW('m', 1, combo_dev_attr_t))

The combo_dev_attr_t is built with:

  • input_mode = 0 (MIPI — correct, taken from .ini input_mode)
  • mipi_dev_attr.raw_data_type = 0uninitialized / not from .ini data_type
  • mipi_dev_attr.lane_id[] = all zeros / unset ← not from .ini lane_id

Kernel rejects raw_data_type = 0 with invalid raw_data_type, must be in [2,5). Valid values are RAW_DATA_10BIT=2, RAW_DATA_12BIT=3, RAW_DATA_14BIT=4.

The .ini has these fields populated (after #2155 lands on cv200) — they should drive the struct.

2. VIU_DEV_ATTR_SET (ioctl 0x40804900)

The VI_DEV_ATTR_S arrives with enIntfMode != VI_MODE_MIPI. Vendor firmware sets enIntfMode = 5 (VI_MODE_MIPI) and au32CompMask[0] = 0xfff00000 (10-bit data on bits 12-21). Majestic uses the default initializer / a value appropriate for parallel sensors, even when .ini input_mode = 0.

What the shim does

// HI_MIPI_SET_DEV_ATTR — fix raw_data_type + lane_id
if (combo_dev_attr.input_mode == 0 /* MIPI */) {
    combo_dev_attr.mipi_dev_attr.raw_data_type = 2;          // RAW_DATA_10BIT
    combo_dev_attr.mipi_dev_attr.lane_id[0..1] = {0, 1};     // 2-lane
    combo_dev_attr.mipi_dev_attr.lane_id[2..7] = {-1, ...};  // disabled
}

// VIU_DEV_ATTR_SET — fix enIntfMode + comp mask
if (intf != 5) {
    vi_dev_attr.enIntfMode = 5;                              // VI_MODE_MIPI
    vi_dev_attr.au32CompMask[0] = 0xfff00000;                // RAW10 alignment
}

After the shim is loaded: /proc/driver/hi_mipi flips to LaneNum=2 RAW10 MIPI, mipi int IRQs fire, ISP IRQs climb, VI receives frames, RTSP serves clean H.264 1080p.

Suggested fix

For MIPI sensors (input_mode = 0), majestic should populate combo_dev_attr.mipi_dev_attr from the .ini's [mipi] section:

  • raw_data_type[mipi] data_type (RAW_DATA_* enum, .ini values match the kernel enum exactly)
  • lane_id[][mipi] lane_id (pipe-separated, -1 = disable)

And the VI enIntfMode / au32CompMask should be derived from [mode] input_mode and [mipi] data_type respectively (the comp-mask values are standard per RAW bit-width on cv200).

cv300 already works because its ov2735_i2c_1080p.ini has correct values and its majestic build appears to respect them; cv200 majestic does not.

Hardware / repro

  • Camera: TP-Link Kasa KC110 (Hi3518EV200, OV2735 MIPI 2-lane, RTL8188FU). Same symptom probably affects other Hi3518EV200 + OV2735 cameras.
  • Firmware: OpenIPC hi3518ev200_ultimate, with OpenIPC/firmware#2154 and #2155 (load_hisilicon ov2735 case + .ini fixes — without those the sensor doesn't even reach the MIPI ioctl stage).
  • Workaround: LD_PRELOAD shim (source). Reproducible by unset LD_PRELOAD; /etc/init.d/S95majestic restart — symptoms return instantly.

Context

Came out of a longer reverse-engineering effort to bring up OV2735 on Hi3518EV200 (full diagnostic writeup here). Happy to provide more disasm / register dumps if useful. The shim is intentionally not being upstreamed — flagged as such in the closed OpenIPC/firmware#2152 where @widgetii correctly pointed out that the right fix lives here in majestic.

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